1. Field of the Invention
The present invention relates to a power supply generating system and in particular to a power supply generating system which can adapt a power save mode useful for, for example, a driving section of a display device.
2. Description of the Related Art
Flat panel display devices such as a liquid crystal and an organic EL display devices are generally thin, lightweight, and consume less power. Because of these characteristics, flat panel display devices are suited for use as display devices for portable devices, such as mobile phones, and have therefore come to be widely employed in many such portable devices.
FIG. 1 shows a structure of a liquid crystal display device used as a display device in a mobile phone. The liquid crystal display device comprises a liquid crystal display (LCD) panel 200 constructed by sealing liquid crystals between a pair of substrates, a driving circuit 101 for driving the LCD panel 200, and a power source circuit 350 for supplying the required supply voltage to the driving circuit 101 and LCD panel 200.
The driving circuit 101 comprises a latch circuit 10 for latching supplied RGB digital data, a D/A converter circuit 12 for converting the latched digital data to analog data, and an amplifier 14 for amplifying the converted analog data and supplying to the liquid crystal display panel 200 R, G, and B analog display data. The driving circuit 101 further comprises a timing controller (T/C) 22 and a CPU interface (I/F) circuit 20 for receiving an instruction from a CPU (not shown) and outputting a control signal in response to the instruction. The T/C 22 generates a timing signal suited for display at the liquid crystal display panel 200 based on timing signals such as a dot clock DOTCLK, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync.
The power supply circuit 350 generates a plurality of supply voltages as necessary. The power supply circuit 350 supplies a supply voltage VDD1 having a low voltage to the latch circuit 10 constructed from a CMOS logical circuit suited for driving at a low voltage, a supply voltage VDD2 having a higher voltage to the D/A converter circuit 12 and amplifier 14, and a supply voltage VDD3 having even higher voltage to the LCD panel 200.
FIG. 2 shows a structure of a related art power supply circuit 350 which is capable of generating the higher voltage VDD2 having a voltage twice that of the input voltage. The power supply circuit 350 is a charge pump type circuit and comprises two capacitors C1 and C2, switches SW1 through SW4 for switching the supply route of the input voltage to the capacitors, an oscillation circuit 35 for generating a pulse signal for controlling the open/close switching of the switches SW1 through SW4, an AND gate 37, and a NAND gate 39. The oscillation circuit 35 generates a pulse signal having, for example, a duty ratio of 1/2. The pulse signal is supplied to the switches SW1 and SW2 via the AND gate 37 and to the switches SW3 and SW4 via the NAND gate 39 such that the switches SW1 and SW2, and SW3 and SW4 are alternately opened and closed. When switches SW3 and SW4 are closed, the input voltage VIN is applied to the electrode of the capacitor C1 at the upper side of the drawing, and the lower electrode becomes the ground (GND). Thus, the capacitor C1 is charged. At the next timing, the switches SW3 and SW4 are opened and the switches SW1 and SW2 are closed. In this case, the input voltage VIN is applied to the lower electrode of the capacitor C1, the voltage at the upper electrode of the capacitor C1 is boosted to a voltage of twice the input voltage VIN, and the output voltage VDD2 having a voltage twice that of the input voltage VIN is obtained at the output end at the point between the upper electrodes of the capacitor C1 and the capacitor C2.
There is a strong demand for reducing the power consumption in portable instruments such as mobile phones and, therefore, in the display devices for such instruments. In order to satisfy this demand, a power save mode, in which the device power supply is controlled to be turned off in order to reduce the power consumption, is commonly employed.
The display device depicted in FIG. 1 also includes the power save mode. The I/F circuit 20 analyzes a power save control instruction transmitted from a CPU (not shown) and generates a power save control signal. The power save control signal may be, for example, a signal having a high level (H level) during normal operation and a low level (L level) during the power save mode, and is supplied to the oscillation circuit 35 of the power supply circuit 350, to one input terminal of the AND gate 37, and to one input terminal of the NAND gate 39, as shown in FIG. 2.
The oscillation circuit 35 of the power supply circuit 350, which receives a power save control signal of H level during the normal operation, generates a pulse signal. Because the power save control signal at H level is supplied to one input terminal of the AND gate 37 and of the NAND gate 39, a pulse signal having the same phase as the pulse signal from the oscillation circuit 35 is output from the AND gate 37, and a pulse signal having the inverted phase of the pulse signal from the oscillation circuit 35 is output from the NAND gate 39. When the power save control signal becomes L level and power save mode is activated, the oscillation circuit 35 halts operation, the output of the AND gate 37 is fixed at the L level, and the output of the NAND gate 39 is fixed at the H level. Because of this, switching operation between the switches SW1 through SW4 is suspended, the capacitors C1 and C2 are discharged, output voltage is reduced, and thus, the power supply circuit 350 is controlled to be turned off.
As described above, by switching off the supply voltage to the driving circuit 101 and to the LCD panel 200, the power consumption at the driving circuit 101 and at the LCD panel 200 is shut down, and, therefore, it is possible to reduce the power consumption at the display device.
In many cases, the driving circuit 101 is integrated onto a single chip IC. The power supply circuit 350, on the other hand, requires capacitors and an oscillation circuit, and thus, needs to be constructed as a separate circuit external to the driving IC 101.
However, in a portable instrument such as a mobile phone, in addition to the reduction in the power consumption, there is simultaneously a strong demand for reduction of the weight, size, thickness, and cost of the devices. In such an environment, an external circuit such as an oscillation circuit 350 creates a large problem because of the area it occupies and because, in order to adapt a power save mode in the power supply circuit 350, the oscillation circuit 35 must include a power save mode capability. Therefore, reduction in the complexity and in the size of the oscillation circuit 35 is limited.